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1 for more information www.linear.com/2314-14 typical a pplica t ion fea t ures descrip t ion 14-bit, 4.5msps serial sampling adc in tsot the lt c ? 2314-14 is a 14-bit, 4.5 msps, serial sampling a/d converter that draws only 6.2 ma from a wide range analog supply adjustable from 2.7 v to 5.25 v. the ltc2314-14 contains an integrated bandgap and reference buffer which provide a low cost, high performance (20 ppm/c max) and space saving applications solution. the ltc2314-14 achieves outstanding ac performance of 77 db sinad and C85db thd while sampling a 500 khz input frequency. the extremely high sample rate-to-power ratio makes the ltc2314-14 ideal for compact, low power, high speed systems. the ltc2314-14 also provides both nap and sleep modes for further optimization of the device power within a system. the ltc2314-14 has a high-speed spi-compatible serial interface that supports 1.8v, 2.5v, 3 v and 5 v logic. the fast 4.5 msps throughput makes the ltc2314-14 ideally suited for a wide variety of high speed applications. a pplica t ions n 4. 5msps throughput rate n guaranteed 14-bit no missing codes n internal reference: 2.048v/4.096v span n low noise: 77.5db snr n low power: 6.2ma at 4.5msps and 5v n dual supply range: 3v/5v operation n sleep mode with < 1a typical supply current n nap mode with quick wake-up < 1 conversion n separate 1.8v to 5v digital i/o supply n high speed spi-compatible serial i/o n guaranteed operation from C 40c to 125c n 8-lead tsot-23 package n communication systems n high speed data acquisition n handheld terminal interface n medical imaging n uninterrupted power supplies n battery operated systems n automotive l, lt , lt c , lt m , linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. 5v supply, internal reference, 4.5msps, 14-bit sampling adc serial data link to asic, pld, mpu, dsp or shift registers analog input 0v to 4.096v 5v 2.2f 2.2f 2.2f 231414 ta01 gnd v dd ref a in ov dd sck cs sdo ltc2314-14 digital output supply 1.8v to 5v f s = 4.5msps, f in = 500khz 32k-pt fft 231414 ta01a frequency (khz) amplitude (dbfs) 0 2250 1750 2000 750 1000 500250 1250 1500 0 ?20 ?40 ?60 ?80 ?100 ?120 ?160 ?140 v dd = 5v snr = 77.5dbfs sinad = 76.9dbfs thd = 84.9db sfdr = 88.1db ltc 2314-14 231414f
2 for more information www.linear.com/2314-14 p in c on f igura t ion a bsolu t e maxi m u m r a t ings supply voltage (v dd , ov dd ) ....................................... 6v ref erence ( ref ) and analog input (a in ) voltage ( note 3) ...................................... (C 0.3 v) to (v dd + 0.3 v) digital input voltage ................ (C0.3 v) to ( ov dd + 0.3 v) digital output voltage ............. (C 0.3 v) to ( ov dd + 0.3 v) power dissipation ............................................... 10 0 mw operating temperature range ltc 2 314 c ................................................ 0 c to 70 c ltc 2 314 i.............................................. C40 c to 85 c ltc 2 314 h .......................................... C 40 c to 125 c storage temperature range .................. C 65 c to 150 c lead temperature range ( soldering , 10 sec ) ........ 30 0 c (notes 1, 2) 1 2 3 4 8 7 6 5 top view ts8 package 8-lead plastic tsot-23 cs sck sdo ov dd v dd ref gnd a in t jmax = 145c, ja = 195c/w o r d er i n f or m a t ion lead free finish tape and reel (mini) tape and reel part marking* package description temperature range ltc2314cts8-14#trmpbf ltc2314cts8-14#trpbf ltfzf 8-lead plastic tsot-23 0c to 70c ltc2314its8-14#trmpbf ltc2314its8-14#trpbf ltfzf 8-lead plastic tsot-23 C40?c to 85?c ltc2314hts8-14#trmpbf ltc2314hts8-14#trpbf ltfzf 8-lead plastic tsot-23 C40?c to 125?c trm = 500 pieces. *temperature grades are identified by a label on the shipping container. consult lt c marketing for parts specified with wider operating temperature ranges. consult lt c marketing for information on lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ ltc 2314-14 231414f
3 for more information www.linear.com/2314-14 e lec t rical c harac t eris t ics conver t er c harac t eris t ics d y n a m ic accuracy symbol parameter conditions min typ max units v ain absolute input range l C0.05 v dd + 0.05 v v in input voltage range (note 12) 0 v ref v i in analog input dc leakage current l C1 1 a c in analog input capacitance sample mode hold mode 13 3 pf pf symbol parameter conditions min typ max units resolution l 14 bits no missing codes l 14 bits transition noise (note 7) 0.7 lsb rms inl integral linearity error v dd = 5v (notes 5, 6) v dd = 3v (notes 5, 6) l l C3.75 C4.25 1 1.5 3.75 4.25 lsb lsb dnl differential linearity error v dd = 5v (note 6) v dd = 3v (note 6) l l C0.99 C0.99 0.3 0.4 0.99 0.99 lsb lsb offset error v dd = 5v (note 6) v dd = 3v (note 6) l l C9 C22 2 4 9 22 lsb lsb full -scale error v dd = 5v (note 6) v dd = 3v (note 6) l l C18 C26 5 7 18 26 lsb lsb t otal unadjusted error v dd = 5v (note 6) v dd = 3v (note 6) l l C22 C30 6 8 22 30 lsb lsb symbol parameter conditions min typ max units sinad signal-to-(noise + distortion) ratio f in = 500khz, v dd = 5v f in = 500khz, v dd = 3v l l 72 69 77 72.6 db db snr signal -to-noise ratio f in = 500khz, v dd = 5v f in = 500khz, v dd = 3v l l 73 69.5 77.5 73 db db thd t otal harmonic distortion first 5 harmonics f in = 500khz, v dd = 5v f in = 500khz, v dd = 3v l l C85 C85 C75 C74 db db sfdr spurious free dynamic range f in = 500khz, v dd = 5v f in = 500khz, v dd = 3v l l C87 C87 C77 C75 db db imd intermodulation distortion 2nd order t erms 3rd order terms f in1 = 461khz, f in2 = 541khz a in1 , a in2 = C7dbfs C79.4 C90.8 dbc dbc full power bandwidth at 3db at 0.1db 130 20 mhz mhz C3db input linear bandwidth sinad 72db 5 mhz t ap aperture delay 1 ns t jitter aperture jitter 10 ps the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c and a in = C1dbfs. (note 4) ltc 2314-14 231414f
4 for more information www.linear.com/2314-14 re f erence inpu t / ou t pu t power require m en t s d igi t al inpu t s an d d igi t al ou t pu t s symbol parameter conditions min typ max units v ref v ref output voltage 2.7v v dd 3.6v 4.75 v dd 5.25v l l 2.040 4.080 2.048 4.096 2.056 4.112 v v v ref temperature coefficient l 7 20 ppm/c v ref output resistance normal operation overdrive condition (v refin v refout + 50mv) 2 52 k v ref line regulation 2.7v v dd 3.6v 4.75 v dd 5.25v 0.4 0.2 mv/v mv/v v ref 2.048/4.096 supply threshold 4.15 v v ref 2.048/4.096 supply threshold hysteresis 150 mv v ref input voltage range (external reference input) 2.7 v v dd 3.6v 4.75 v dd 5.25v l l v ref + 50mv v ref + 50mv v dd 4.3 v v symbol parameter conditions min typ max units v dd supply voltage 3v operational range 5v operational range l l 2.7 4.75 3 5 3.6 5.25 v v ov dd digital output supply voltage l 1.71 5.25 v i total = i vdd + i ovdd supply current, static mode operational mode nap mode sleep mode cs = 0v, sck = 0v v dd = 5v, ov dd = 1.8v, f smpl = 4.5msps l l l 3.2 6.2 1.8 0.8 4 7.2 5 ma ma ma a p d power dissipation, static mode operational mode nap mode sleep mode cs = 0v, sck = 0v v dd = 5v, ov dd = 1.8v, f smpl = 4.5msps l l l 16 31 9 4 20 36 25 mw mw mw w symbol parameter conditions min typ max units v ih high level input voltage l 0.8 ? ov dd v v il low level input voltage l 0.2 ? ov dd v i in digital input current v in = 0v to ov dd l C10 10 a c in digital input capacitance 5 pf v oh high level output voltage i o = C500a (source) l ov dd C0.2 v v ol low level output voltage i o = 500a (sink) l 0.2 v i oz high-z output leakage current v out = 0v to ov dd , cs = high l C10 10 a c oz high-z output capacitance cs = high 4 pf i source output source current v out = 0v, ov dd = 1.8v C20 ma i sink output sink current v out = ov dd = 1.8v 20 ma the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) ltc 2314-14 231414f
5 for more information www.linear.com/2314-14 a d c t i m ing charac t eris t ics symbol parameter conditions min typ max units f sample(max) maximum sampling frequency (notes 8, 9) l 4.5 mhz f sck shift clock frequency (notes 8, 9) l 87.5 mhz t sck shift clock period l 11.4 ns t throughput minimum throughput time, t acq + t conv l 222 ns t conv conversion time l 182 ns t acq acquisition time l 40 ns t 1 minimum cs pulse width (note 8) l 10 ns t 2 sck ? setup time after cs (note 8) l 5 ns t 3 sdo enable time after cs (notes 8, 9) l 6 ns t 4 sdo data valid access time after sck (notes 8, 9, 10) l 9.1 ns t 5 sclk low time l 4.5 ns t 6 sclk high time l 4.5 ns t 7 sdo data valid hold time after sck (notes 8, 9, 10) l 1 ns t 8 sdo into hi-z state time after 16th sck (notes 8, 9) l 3 6 ns t 9 sdo into hi-z state time after cs (notes 8, 9) l 3 6 ns t 10 cs setup time after 14th sck (note 8) l 5 ns latency l 1 cycle latency t wake _ nap power-up time from nap mode see nap mode section 50 ns t wake _ sleep power-up time from sleep mode see sleep mode section 1.1 ms the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) note 1. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2 . all voltage values are with respect to ground. note 3. when these pin voltages are taken below ground or above v dd (a in , ref) or ov dd (sck, cs, sdo) they will be clamped by internal diodes. this product can handle input currents up to 100ma below ground or above v dd or ov dd without latch-up. note 4. v dd = 5v, ov dd = 2.5v, f smpl = 4.5mhz, f sck = 87.5mhz, a in = C1dbfs and internal reference unless otherwise noted. note 5. integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 6. linearity, offset and gain specifications apply for a single-ended a in input with respect to ground. note 7. typical rms noise at code transitions. note 8. parameter tested and guaranteed at ov dd = 2.5v. all input signals are specified with t r = t f = 1ns (10% to 90% of ov dd ) and timed from a voltage level of ov dd /2. note 9. all timing specifications given are with a 10pf capacitance load. load capacitances greater than this will require a digital buffer. note 10. the time required for the output to cross the v ih or v il voltage. note 11. guaranteed by design, not subject to test. note 12. recommended operating conditions. ltc 2314-14 231414f
6 for more information www.linear.com/2314-14 typical p er f or m ance c harac t eris t ics 32k point fft f s = 4.5msps f in = 500khz snr, sinad vs input frequency (100khz to 2.2mhz) thd, harmonics vs input frequency (100khz to 2.2mhz) thd, harmonics vs input frequency (100khz to 2.2mhz) snr, sinad vs temperature, f in = 500khz thd, harmonics vs temperature , f in = 500khz integral nonlinearity vs output code differential nonlinearity vs output code dc histogram near mid-scale (code 8192) t a = 25c , v dd = 5v , ov dd = 2.5v , f smpl = 4.5msps, unless otherwise noted. output code 0 ?1.00 ?0.75 ?0.50 dnl (lsb) ?0.25 0.25 0.00 0.50 0.75 1.00 4096 8192 12288 16384 231414 g02 231414 g04 input frequency (khz) amplitude (dbfs) 0 2250 1750 2000 750 1000 500250 1250 1500 0 ?20 ?40 ?60 ?80 ?100 ?120 ?160 ?140 v dd = 5v snr = 77.5dbfs sinad = 76.9dbfs thd = 84.9db sfdr = 88.1db input frequency (khz) 0 72 73 snr, sinad (dbfs) 75 74 76 77 78 500250 750 1000 1250 1500 20001750 2250 231414 g05 sinad snr sinad snr v dd = 5v v dd = 3v input frequency (khz) 0 ?105 ?95 ?100 thd, harmonics (db) ?90 ?85 ?80 ?75 500250 750 1000 1250 1500 20001750 2250 231414 g06 thd 2nd 3rd r in /c in = 50/47pf f s = 4.5msps v dd = 3v temperature (c) ?55 ?35 71 74 73 72 snr, sinad (dbfs) 75 76 78 77 79 ?15 5 25 45 65 85 105 125 231414 g07 snr snr sinad sinad v dd = 5v v dd = 3v temperature (c) ?55 ?35 ?100 ?95 thd, harmonics (db) ?90 ?85 ?80 ?75 ?15 5 25 45 65 85 105 125 231414 g08 thd 3rd 2nd v dd = 3v output code 0 ?2.0 ?1.0 ?1.5 inl (lsb) ?0.5 0.5 0.0 1.0 1.5 2.0 4096 8192 12288 16384 231414 g01 input frequency (khz) 0 ?105 ?95 ?100 thd, harmonics (db) ?90 ?85 ?80 ?75 500250 750 1000 15001250 20001750 2250 231414 g06a thd 2nd 3rd r in /c in = 50/47pf f s = 4.5msps v dd = 5v 8195 8198 8199 8200 = 0.7 0 2000 1000 3000 4000 5000 7000 6000 ltc 2314-14 231414f code 8194 counts 8196 8197 231414 g03
7 for more information www.linear.com/2314-14 typical p er f or m ance c harac t eris t ics supply current vs temperature shutdown current vs temperature supply current vs sck frequency reference current vs reference voltage full-scale error vs temperature offset error vs temperature snr, sinad vs reference voltage f in = 500khz thd, harmonics vs temperature, f in = 500khz t a = 25c , v dd = 5v , ov dd = 2.5v , f smpl = 4.5msps, unless otherwise noted. reference voltage (v) 2 72 snr, sinad (dbfs) 75 74 73 77 76 79 78 2.5 3 3.5 4 4.5 231414 g10 snr snr sinad sinad v dd = 3.6v operation not allowed v dd = 5v reference voltage (v) 2 0 reference current (a) 200 100 300 400 500 600 2.5 3 3.5 4 4.5 231414 g11 v dd = 3.6v f s = 5msps f s = 5msps f s = 3msps f s = 3msps operation not allowed v dd = 5v temperature (c) ?55 ?4 full-scale error (lsb) ?1 0 ?3 ?2 1 2 3 4 ?35 ?15 5 4525 8565 105 125 231414 g12 temperature (c) ?55 ?1 offset error (lsb) 0 ?0.5 0.5 1 ?35 ?15 5 4525 8565 105 125 231414 g13 temperature (c) ?55 5 supply current (ma) 5.75 5.5 5.25 6 6.5 6.25 ?35 ?15 5 4525 8565 105 125 231414 g14 v dd = 5v v dd = 3v temperature (c) ?55 5 shutdown current (a) 0.25 0.5 1 0.75 ?35 ?15 5 4525 8565 105 125 231414 g15 v dd = 5v v dd = 3v i vdd + i ovdd sck frequency (mhz) 10 0 supply current (ma) 2 4 7 5 3 1 6 20 30 5040 7060 80 90 231414 g16 i tot i vdd v dd = 3v ov dd = 1.8v i ovdd temperature (c) ?55 ?35 ?100 ?95 thd, harmonics (db) ?90 ?85 ?80 ?75 ?15 5 25 45 65 85 105 125 231414 g08a thd 3rd 2nd v dd = 5v ltc 2314-14 231414f
8 for more information www.linear.com/2314-14 t a = 25c , v dd = 5v , ov dd = 2.5v , f smpl = 4.5msps, unless otherwise noted. p in func t ions v dd (pin 1): power supply. the ranges of v dd are 2.7v to 3.6 v and 4.75 v to 5.25 v. bypass v dd to gnd with a 2.2f ceramic chip capacitor. ref (pin 2): reference input/ output. the ref pin volt - age defines the input span of the adc, 0 v to v ref . by default, ref is an output pin and produces a reference voltage v ref of either 2.048 v or 4.096 v depending on v dd ( see table 2). bypass to gnd with a 2.2 f , low esr, high quality ceramic chip capacitor. the ref pin may be overdriven with a voltage at least 50mv higher than the internal reference voltage output. gnd (pin 3): ground. the gnd pin must be tied directly to a solid ground plane. a in ( pin 4): analog input. a in is a single-ended input with respect to gnd with a range from 0v to v ref . ov dd (pin 5): i/o interface digital power. the ov dd range is 1.71 v to 5.25 v. this supply is nominally set to the same supply as the host interface (1.8v, 2.5v, 3.3 v or 5v). bypass to gnd with a 2.2 f ceramic chip capacitor. sdo (pin 6): serial data output. the a/d conversion result is shifted out on sdo as a serial data stream with the msb first through the lsb last. there is 1 cycle of conversion latency. logic levels are determined by ov dd . sck (pin 7): serial data clock input. the sck serial clock falling edge advances the conversion process and outputs a bit of the serialized conversion result, msb first to lsb last. sdo data transitions on the falling edge of sck. a continuous or burst clock may be used. logic levels are determined by ov dd . cs (pin 8): chip select input. this active low signal starts a conversion on the falling edge and frames the serial data transfer. bringing cs high places the sample-and-hold into sample mode and also forces the sdo pin into high impedance. logic levels are determined by ov dd . output supply current (i ovdd ) vs output supply voltage (ov dd ) output supply voltage (v) 1.7 0 output supply current (ma) 0.5 1.0 2.5 2.0 1.5 2.92.3 4.13.5 4.7 5.3 231414 g18 5msps f sck = 87.5mhz 3msps f sck = 52.5mhz supply current (i vdd ) vs supply voltage (v dd ) supply voltage (v) 2.6 4.50 supply current (ma) 5.25 5.00 4.75 5.50 5.75 6.00 6.50 6.25 2.9 3.83.53.2 4.1 4.74.4 5.35.0 231414 g17 5msps f sck = 87.5mhz 3msps f sck = 52.5mhz operation not allowed 5msps 3msps typical p er f or m ance c harac t eris t ics ltc 2314-14 231414f
9 for more information www.linear.com/2314-14 t i m ing diagra ms 231414 td04 231414 td03 231414 td02 231414 td01 hi-z sck ov dd /2 sdo t 8 16th edge hi-z cs ov dd /2 sdo t 9 v ih v il sck ov dd /2 sdo t 7 v oh v ol sck ov dd /2 sdo t 4 figure 1. sdo into hi-z after 16th sck figure 3. sdo data valid hold after sck figure 2. sdo into hi-z after cs figure 4. sdo data valid access after sck b lock diagra m 231414 bd 4 ? + s/h 2.5v ldo 2/4 1.024v bandgap timing logic 1 6 7 8 three-state serial output port 14-bit sar adc 2 3 a in ref v dd ov dd 2.2f gnd analog input range 0v to v ref analog supply range 2.7v to 5.25v digital supply range 1.71v to 5.25v 5 2.2f 2.2f sdo sck cs ts8 package all capacitors unless noted are high quality, ceramic chip type ltc 2314-14 231414f
10 for more information www.linear.com/2314-14 a pplica t ions i n f or m a t ion overview the ltc2314-14 is a low noise, high speed , 14- bit succes- sive approximation register ( sar) adc. the ltc2314-14 operates over a wide supply range (2.7 v to 5.25 v) and provides a low drift (20 ppm/c maximum), internal refer - ence and reference buffer. the internal reference buffer is automatically configured to a 2.048 v span in low supply range (2.7 v to 3.6 v) and to a 4.096 v span in the high supply range (4.75 v to 5.25 v). the ltc2314-14 samples at a 4.5 msps rate and supports an 87.5 mhz data clock. the ltc2314-14 achieves excellent dynamic performance (77db sinad , 85 db thd) while dissipating only 31mw from a 5v supply at the 4.5msps conversion rate. the ltc2314-14 outputs the conversion data with one cycle of conversion latency on the sdo pin. the sdo pin output logic levels are supplied by the dedicated ov dd supply pin which has a wide supply range (1.71 v to 5.25v) allowing the ltc2314-14 to communicate with 1.8v, 2.5v, 3v or 5v systems. the ltc2314-14 provides both nap and sleep power- down modes through serial interface control to reduce power dissipation during inactive periods. serial interface the lt2314-14 communicates with microcontrollers, dsps and other external circuitry via a 3- wire interface. a falling cs edge starts a conversion and frames the serial data transfer. sck provides the conversion clock for the current sample and controls the data readout on the sdo pin of the previous sample. cs transitioning low clocks out the first leading zero and subsequent sck falling edges clock out the remaining data as shown in figures 5, 6 and 7 for three different timing schemes. data is serially output msb first through lsb last, followed by trailing zeros if further sck falling edges are applied. figure 5 illustrates that dur - ing the case where sck is held low during the acquisition phase, only one leading zero is output. figures 6 and 7 illustrate that for the sck held high during acquisition or continuous clocking mode two leading zeros are output. leading zeros allow the 14- bit data result to be framed with both leading and trailing zeros for timing and data verification. since the rising edge of sck will be coincident with the falling edge of cs , delay t 2 is the delay to the first falling edge of sck, which is simply 0.5 ? t sck . delays t 2 (cs falling edge to sck leading edge) and t 10 (16 th falling sck edge to cs rising edge) must be observed for figures 5, 6 and 7 and any timing implementation in order for the conversion process and data readout to occur correctly. the user can bring cs high after the 16 th falling sck edge provided that timing delay t 10 is observed. prematurely terminating the conversion by bringing cs high before the 16th falling sck edge plus delay t 10 will cause a loss of conversion data for that sample. the sample-and-hold is placed in sample mode when cs is brought high. as shown in figure 6, a sample rate of 4.5 msps can be achieved on the ltc2314-14 by using an 87.5 mhz sck data clock and a minimum acquisition time of 40 ns which results in the minimum throughput time (t throughput ) of 222ns. note that the maximum throughput of 4.5 msps can only be achieved with the timing implementation of sck held high during acquisition as shown in figure 6. the ltc2314-14 also supports a continuous data clock as shown in figure 7. with a continuous data clock the acquisition time period and conversion time period must be designed as an exact integer number of data clock periods. because the minimum acquisition time is not an exact multiple of the minimum sck period, the maximum sample rate for the continuous sck timing is less than 4.5msps. for example, a 4.375msps throughput is achieved using exactly 20 data clock periods with the maximum data clock frequency of 87.5 mhz. for this particular case, the acquisition time period and conversion clock period are designed as 4 data clock periods (t acq = 45.7 ns) and 16data clock periods (t conv = 182.9 ns) respectively, yielding a throughput time of 228.6ns. the following table illustrates the maximum throughput achievable for each of the three timing patterns. note that in order to achieve the maximum throughput rate of 4.5msps, the timing pattern where sck is held high during the acquisition time must be used. table 1: maximum throughput vs timing pattern timing pattern maximum throughput sck high during t acq 4.5msps sck low during t acq 4.375msps sck continuous (t throughput = 20 periods) 4.375msps ltc 2314-14 231414f
11 for more information www.linear.com/2314-14 t throughput t acq-min t acq-min = 40ns t conv t conv(min) = 15 ? t sck + t 2 + t 10 16 15 54321 cs sck sdo hi-z state (msb) *note: sdo represents the analog input from the previous conversion b0 0 b1 b11 b12 b13* 00 231414 td06 t 5 t 6 t 2 t 4 t 7 t 10 t 9 t 3 figure 6: ltc2314-14 serial interface timing diagram (sck high during t acq ) t throughput = 20 ? t sck t acq t acq = 4 ? t sck t conv t conv = 16 ? t sck 15 16 17 18 19 20 20 4 5 321 cs sck sdo hi-z state (msb) *note: sdo represents the analog input from the previous conversion b1 b0 0 b11 b12 b13* 00 231414 td07 t 5 t 6 t 2 t 4 t 7 t 10 t 9 t 3 figure 7: ltc2314-14 serial interface timing diagram (sck continuous) a pplica t ions i n f or m a t ion t throughput t acq-min t acq-min = 40ns t conv t conv = 15.5 ? t sck + t 2 + t 10 1615 144321 cs sck sdo hi-z state (msb) *note: sdo represents the analog input from the previous conversion b0 0 b11 b12 b13* 0 231414 f05 t 5 t 6 t 2 t 4 t 7 t 9 t 3 t 10 figure 5: ltc2314-14 serial interface timing diagram (sck low during t acq ) serial data output (sdo) the sdo output is always forced into the high impedance state while cs is high. the falling edge of cs starts the conversion and enables sdo. the a/d conversion result is shifted out on the sdo pin as a serial data stream with the msb first. the data stream consists of either one leading zero ( sck held low during acquisition, fig. 5) or two leading zeros ( sck held high during acquisition, fig. 6) followed by 14 bits of conversion data. there is 1 cycle of conversion latency. subsequent falling sck edges after the lsb is output will output zeros on the sdo pin. the sdo output returns to the high impedance state after the 16th falling edge of sck. ltc 2314-14 231414f
12 for more information www.linear.com/2314-14 a pplica t ions i n f or m a t ion the output swing on the sdo pin is controlled by the ov dd pin voltage and supports a wide operating range from 1.71 v to 5.25 v independent of the v dd pin voltage. power considerations the ltc2314-14 provides two sets of power supply pins : the analog 5 v power supply (v dd ) and the digital input/ output interface power supply (ov dd ). the flexible ov dd supply allows the ltc2314-14 to communicate with any digital logic operating between 1.8 v and 5 v, including 2.5v and 3.3v systems. entering nap/sleep mode pulsing cs two times and holding sck static places the ltc2314-14 into nap mode. pulsing cs four times and holding sck static places the ltc2314-14 into sleep mode. in sleep mode, all bias circuitry is shut down, including the internal bandgap and reference buffer, and only leakage currents remain (0.8 a typical). because the reference buffer is externally bypassed with a large capacitor (2.2f ), the ltc2314-14 requires a significant wait time (1.1 ms) to recharge this capacitance before an accurate conversion can be made. in contrast, nap mode does not power down the internal bandgap or reference buffer allowing for a fast wake- up and accurate conversion within one conversion clock cycle. supply current during nap mode is nominally 1.8ma. figure 8: ltc2314-14 entering/exiting nap mode figure 9: ltc2314-14 entering/exiting sleep mode cs sck z 1 2 z sdo hi-z state 231414 f08 nap mode hold static high or low hold static high or low start t acq 0 0 cs sck 1 2 z z 3 4 sdo hi-z state 231414 f09 nap mode sleep mode hold static high or low start t acq v ref recovery 0 0 t wait exiting nap/sleep mode waking up the ltc2314-14 from either nap or sleep mode, as shown in figures 8 and 9, requires sck to be pulsed one time. a conversion may be started immediately fol - lowing nap mode as shown in figure 8. a period of time allowing the reference voltage to recover must follow waking up from sleep mode as shown in figure 9. the wait period required before initiating a conversion for the recommended value of c ref of 2.2f is 1.1ms. power supply sequencing the ltc2314-14 does not have any specific power sup - ply sequencing requirements. care should be taken to observe the maximum voltage relationships described in the absolute maximum ratings section. single-ended analog input drive the analog input of the ltc2314-14 is easy to drive. the input draws only one small current spike while charging the sample-and-hold capacitor at the end of conversion. during the conversion, the analog input draws only a small leakage current. if the source impedance of the driving circuit is low, then the input of the ltc2314-14 can be driven directly. as the source impedance increases, so will the acquisition time. for minimum acquisition time ltc 2314-14 231414f
13 for more information www.linear.com/2314-14 a pplica t ions i n f or m a t ion with high source impedance, a buffer amplifier should be used. the main requirement is that the amplifier driving the analog input must settle after the small current spike before the next conversion starts. settling time must be less than t acq-min (40 ns) for full performance at the maximum throughput rate. while choosing an input amplifier, also keep in mind the amount of noise and harmonic distortion the amplifier contributes. choosing an input amplifier choosing an input amplifier is easy if a few requirements are taken into consideration. first, to limit the magnitude of the voltage spike seen by the amplifier from charging the sampling capacitor, choose an amplifier that has a low output impedance (<50) at the closed-loop bandwidth frequency. for example, if an amplifier is used in a gain of 1 and has a unity-gain bandwidth of 100 mhz, then the output impedance at 100 mhz must be less than 50. the second requirement is that the closed-loop bandwidth must be greater than 100 mhz to ensure adequate small signal settling for full throughput rate. if slower op amps are used, more time for settling can be provided by in - creasing the time between conversions. the best choice for an op amp to drive the ltc2314-14 will depend on the application. generally, applications fall into two categories: ac applications where dynamic specifications are most critical and time domain applications where dc accuracy and settling time are most critical. the following list is a summary of the op amps that are suitable for driving the ltc2314-14. ( more detailed information is available on the linear technology website at www.linear.com.) lt6230: 215 mhz gbwp, C80 dbc distortion at 1mhz, unity-gain stable, rail-to-rail input and output , 3.5ma/ amplifier, 1.1nv/ hz. lt6200 : 165 mhz gbwp , C85 dbc distortion at 1 mhz, unity - gain stable, r-r in and out , 15ma/amplifier, 0.95nv/ hz. lt1818/1819: 400mhz gbwp, C85dbc distortion at 5 mhz, unity-gain stable , 9 ma/amplifier, single/dual voltage mode operational amplifier. input drive circuits the analog input of the ltc2314-14 is designed to be driven single- ended with respect to gnd. a low impedance source can directly drive the high impedance analog input of the ltc2314-14 without gain error. a high impedance source should be buffered to minimize settling time during acquisi - tion and to optimize the distortion performance of the adc. for best performance, a buffer amplifier should be used to drive the analog input of the ltc2314-14. the amplifier provides low output impedance to allow for fast settling of the analog signal during the acquisition phase. it also provides isolation between the signal source and the adc inputs which draw a small current spike during acquisition. input filtering the noise and distortion of the buffer amplifier and other circuitry must be considered since they add to the adc noise and distortion. noisy input circuitry should be filtered prior to the analog inputs to minimize noise. a simple 1-pole rc filter is sufficient for many applications. large filter rc time constants slow down the settling at the analog inputs. it is important that the overall rc time constants be short enough to allow the analog inputs to completely settle to >12-bit resolution within the minimum acquisition time (t acq-min ) of 40ns. a simple 1- pole rc filter is sufficient for many applications . for example, figure 10 shows a recommended single- ended buffered drive circuit using the lt1818 in unity gain mode. the 47 pf capacitor from a in to ground and 50 source resistor limits the input bandwidth to 68 mhz. the 47pf capacitor also acts as a charge reservoir for the input sample-and-hold and isolates the lt1818 from sampling glitch kick-back. the 50 source resistor is used to help stabilize the settling response of the drive amplifier. when choosing values of source resistance and shunt capaci - tance, the drive amplifier data sheet should be consulted and followed for optimum settling response. if lower input bandwidths are desired, care should be taken to optimize the settling response of the driver amplifier with higher values of shunt capacitance or series resistance. high quality capacitors and resistors should be used in the rc filter since these components can add distortion. np0/ c0g and silver mica type dielectric capacitors have excellent linearity. carbon surface mount resistors can generate distortion from self heating and from damage that may occur during soldering. metal film surface mount resistors ltc 2314-14 231414f
14 for more information www.linear.com/2314-14 a pplica t ions i n f or m a t ion are much less susceptible to both problems. when high amplitude unwanted signals are close in frequency to the desired signal frequency, a multiple pole filter is required. high external source resistance, combined with external shunt capacitance at pin 4 and 13pf of input capacitance on the ltc2314-14 in sample mode, will significantly reduce the internal 130mhz input bandwidth and may increase the required acquisition time beyond the minimum acquisition time (t acq-min ) of 40ns. table 2: reference voltage vs supply range supply voltage (v dd ) ref voltage (v ref ) 2.7v C> 3.6v 2.048v 4.75v C> 5.25v 4.096v 47pf 50 231414 f10 a in ltc2314-14 lt1818 gnd analog in + ? figure 10. rc input filter adc reference a low noise, low temperature drift reference is critical to achieving the full data sheet performance of the adc . the ltc2314-14 provides an excellent internal reference with a guaranteed 20ppm/ c maximum temperature coefficient. for added flexibility, an external reference may also be used. the high speed, low noise internal reference buffer is used only in the internal reference configuration. the reference buffer must be overdriven in the external reference con - figuration with a voltage 50 mv higher than the nominal reference output voltage in the internal configuration. using the internal reference the internal bandgap and reference buffer are active by default when the ltc2314-14 is not in sleep mode. the reference voltage at the ref pin scales automatically with the supply voltage at the v dd pin. the scaling of the refer- ence voltage with supply is shown in table 2. f r om 0 v to 2.048 v . an analog input voltage that goes below 0v will be coded as all zeros and an analog input voltage that exceeds 2.048v will be coded as all ones. it is recommended that the ref pin be bypassed to ground with a low esr , 2.2 f ceramic chip capacitor for optimum performance. external reference an external reference can be used with the ltc2314-14 if better performance is required or to accommodate a larger input voltage span. the only constraints are that the external reference voltage must be 50 mv higher than the internal reference voltage ( see table 2) and must be less than or equal to the supply voltage (or 4.3 v for the 5v supply range). for example, a 3.3 v external reference may be used with a 3.3 v v dd supply voltage to provide a 3.3v analog input voltage span (i.e. 3.3v > 2.048v + 50mv). or alternatively, a 2.5 v reference may be used with a 3v supply voltage to provide a 2.5 v input voltage range (i.e. 2.5v > 2.048v + 50 mv). the ltc6655-3.3, ltc6655-2.5, available from linear technology, may be suitable for many applications requiring a high performance external reference for either 3.3 v or 2.5 v input spans respectively. transfer function figure 11 depicts the transfer function of the ltc2314-14. the code transitions occur midway between successive integer lsb values (i.e. 0.5lsb, 1.5lsb, 2.5 lsb fs- 0.5lsb). the output code is straight binary with 1lsb = v ref /16,384. dc performance the noise of an adc can be evaluated in two ways: signal-to-noise ratio ( snr) in the frequency domain and histogram in the time domain. the ltc2314-14 excels in both. the noise in the time domain histogram is the transition noise associated with a 14- bit resolution adc which can be measured with a fixed dc signal applied to the input of the adc. the resulting output codes are collected over a large number of conversions. the shape of the distribution of codes will give an indication of the magnitude of the transition noise. in figure 12, the distri - bution of output codes is shown for a dc input that has the reference voltage also determines the full-scale analog input range of the ltc2314-14. for example, a 2.048 v reference voltage will accommodate an analog input range ltc 2314-14 231414f
15 for more information www.linear.com/2314-14 a pplica t ions i n f or m a t ion signal-to-noise and distortion ratio (sinad) the signal - to - noise and distortion ratio ( sinad) is the ratio be - tween the r ms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components at the a/d output. the output is band- limited to frequencies from above dc and below half the sampling frequency. figure 14 shows the ltc2314-14 maintains a sinad above 74db up to the nyquist input frequency of 2.25mhz. effective number of bits (enob) the effective number of bits ( enob) is a measurement of the resolution of an adc and is directly related to sinad by the equation where enob is the effective number of bits of resolution and sinad is expressed in db: enob = (sinad C 1.76)/6.02 at the maximum sampling rate of 5 mhz, the ltc2314-14 maintains an enob above 12 bits up to the nyquist input frequency of 2.25mhz. (figure 14) signal-to-noise ratio (snr) the signal-to-noise ratio ( snr) is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components except the first five harmonics and dc. figure 13 shows that the ltc2314-14 achieves a typical snr of 77.5db at a 4.5mhz sampling rate with a 500khz input frequency. t otal harmonic distortion (thd) total harmonic distortion ( thd) is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency (f smpl /2). thd is expressed as: thd = 20log v2 2 + v3 2 + v4 2 + v n 2 v1 where v1 is the rms amplitude of the fundamental fre- quency and v 2 through v n are the amplitudes of the second through nth harmonics. thd versus input frequency is shown in the typical performance characteristics section. the ltc2314-14 has excellent distortion performance up to the nyquist frequency. figure 11. ltc2314-14 transfer function input voltage (v) output code 231414 f11 111...111 111...110 000...000 000...001 fs ? 1lsb 0 1lsb been digitized 16,384 times. the distribution is gaussian and the rms code transition noise is 0.7 lsb. this cor- responds to a noise level of 77.5 db relative to a full scale voltage of 4.096v. figure 12. histogram for 16384 conversions 231414 f12 code 8194 counts 8196 8197 8195 8198 8199 8200 = 0.7 0 2000 1000 3000 4000 5000 7000 6000 dynamic performance the ltc2314-14 has excellent high speed sampling capability. fast fourier transform ( fft ) techniques are used to test the adcs frequency response, distortion and noise at the rated throughput. by applying a low distortion sine wave and analyzing the digital output using an fft algorithm, the adcs spectral content can be examined for frequencies outside the applied fundamental. the ltc2314-14 provides guaranteed tested limits for both ac distortion and noise measurements. ltc 2314-14 231414f
16 for more information www.linear.com/2314-14 a pplica t ions i n f or m a t ion intermodulation distortion (imd) if the adc input signal consists of more than one spectral component, the adc transfer function nonlinearity can pro - duce intermodulation distortion ( imd) in addition to thd. imd is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. if two pure sine waves of frequencies f a and f b are ap- plied to the adc input, nonlinearities in the adc transfer function can create distortion products at the sum and difference frequencies m ? f a n ? f b , where m and n = 0, 1, 2, 3, etc. for example, the 2 nd order imd terms include (f a f b ). if the two input sine waves are equal in magnitude, the value ( in decibels) of the 2 nd order imd products can be expressed by the following formula: imd(f a f b ) = 20 ? log[v a (f a f b )/v a (f a )] the ltc2314-14 has excellent imd as shown in figure 15. spurious free dynamic range (sfdr) the spurious free dynamic range is the largest spectral component excluding dc, the input signal and the harmon - ics included in the thd. this value is expressed in decibels relative to the rms value of a full-scale input signal. full -power and full-linear bandwidth the full-power bandwidth is the input frequency at which the amplitude of the reconstructed fundamental is reduced by 3db for a full-scale input signal. the full- linear bandwidth is the input frequency at which the sinad has dropped to 74db (12 effective bits). the ltc2314-14 has been designed to optimize the input band- width, allowing the adc to under- sample input signals with frequencies above the converter s nyquist frequency . the noise floor stays very low at high frequencies and sinad be - comes dominated by di stortion at frequencies beyond nyquist . recommended layout to obtain the best performance from the ltc2314-14 a printed circuit board is required. layout for the printed circuit board ( pcb) should ensure the digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital clocks or signals alongside figure 13. 32k point fft of the ltc2314-14 at f in = 500 khz figure 14. ltc2314-14 enob/sinad vs f in figure 15. ltc2314-14 imd plot 231414 f13 frequency (khz) amplitude (dbfs) 0 2250 1750 2000 750 1000 500250 1250 1500 0 ?20 ?40 ?60 ?80 ?100 ?120 ?160 ?140 v dd = 5v snr = 77.5dbfs sinad = 76.9dbfs thd = 84.9db sfdr = 88.1db input frequency (khz) 0 71 74 73 72 sinad (dbfs) enob 75 76 77 78 11.50 11.67 11.83 12.00 12.17 12.33 12.50 250 500 750 1000 1250 1500 1750 2000 2250 231414 f14 v dd = 5v v dd = 3v input frequency (khz) 0 ?160 ?120 ?140 magnitude (db) ?80 ?100 ?60 ?40 0 ?20 500 1000 1500 2000 2500 231414 f15 v dd = 5v f s = 4.5msps f a = 471.421khz f b = 531.421khz imd 2 (f b + f a ) = ?79.4dbc imd 3 (2fb ?f a ) = ?90.8dbc ltc 2314-14 231414f
17 for more information www.linear.com/2314-14 a pplica t ions i n f or m a t ion figure 16. top silkscreen figure 17. layer 1 top layer figure 18. layer 2 gnd plane analog signals or underneath the adc. the following is an example of a recommended pcb layout. a single solid ground plane is used. bypass capacitors to the supplies are placed as close as possible to the supply pins. low impedance common returns for these bypass capacitors is essential to the low noise operation of the adc. the analog input traces are screened by ground. for more details and information refer to dc1563a , the evaluation kit for the ltc2314-14. bypassing considerations high quality tantalum and ceramic bypass capacitors should be used at the v dd , ov dd and ref pins. for opti- mum per formance, a 2.2 f ceramic chip capacitor should be used for the v dd and ov dd pins. the recommended bypassing for the ref pin is also a low esr , 2.2 f ceramic capacitor. the traces connecting the pins and the bypass capacitors must be kept as short as possible and should be made as wide as possible avoiding the use of vias. the following is an example of a recommended pcb layout. all analog circuitry grounds should be terminated at the ltc2314-14. the ground return from the ltc2314-14 to the power supply should be low impedance for noise free operation. digital circuitry grounds must be connected to the digital supply common. in applications where the adc data outputs and control signals are connected to a continuously active micropro - cessor bus , it is possible to get errors in the conversion results. these errors are due to feed-through from the microprocessor to the successive approximation com - parator. the problem can be eliminated by forcing the microprocessor into a wait state during conversion or by using tri-state buffers to isolate the adc data bus. ltc 2314-14 231414f
18 for more information www.linear.com/2314-14 figure 19. layer 3 pwr plane figure 20. layer 4 bottom layer figure 21. partial 1563a demo board schematic a pplica t ions i n f or m a t ion 4 9v to 10v u5 lt1790acs6-2.048 1 1 ac j4 dc coupling 2 3 2 6 gnd gnd v dd ref csl sck csl sck sdo sdo ov dd vi vo vcm v dd vccio c8 10f c9 4.7f c10 opt c11 opt c12 4.7f c7 opt ref + c6 4.7f r9 1k c18 opt r18 1k 3 1.024v 2.048v hd1x3-100 2 1 c17 1f jp2 v cm r14 0k r15 49.9 r16 33 4 3 231414 f21 1 2 5 8 7 6 u1 * c19 47pf npo jp1 hd1x3-100 a in 0v to 4.096v a in gnd ltc 2314-14 231414f
ltc 2314-14 19 231414f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. 1.50 ? 1.75 (note 4) 2.80 bsc 0.22 ? 0.36 8 plcs (note 3) datum ?a? 0.09 ? 0.20 (note 3) ts8 tsot-23 0710 rev a 2.90 bsc (note 4) 0.65 bsc 1.95 bsc 0.80 ? 0.90 1.00 max 0.01 ? 0.10 0.20 bsc 0.30 ? 0.50 ref pin one id note: 1. dimensions are in millimeters 2. drawing not to scale 3. dimensions are inclusive of plating 4. dimensions are exclusive of mold flash and metal burr 5. mold flash shall not exceed 0.254mm 6. jedec package reference is mo-193 3.85 max 0.40 max 0.65 ref recommended solder pad layout per ipc calculator 1.4 min 2.62 ref 1.22 ref ts8 package 8-lead plastic tsot-23 (reference ltc dwg # 05-08-1637 rev a)
ltc 2314-14 20 231414f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/2314-14 ? linear technology corporation 2013 lt 0213 ? printed in usa r ela t e d p ar t s typical a pplica t ion control logic (fpga, cpld, dsp, etc.) 50 1k 1k 0.1f v cc v cc nc7svu04p5x nl17sz74 nc7svuo4p5x master clock conv enable d pre clr conv q cs sck sdo > ltc2314-14 33 231414 ta03 low-jitter clock timing with rf sine generator using clock squaring/level-shifting circuit and re-timing flip-flop part number description comments adcs ltc1403 / ltc1403 a 12-/14-bit, 2.8msps serial adc 3v, 14mw, unipolar inputs, msop package ltc1403-1/ltc1403 a -1 12-/14-bit, 2.8msps serial adc 3v, 14mw, bipolar inputs, msop package ltc1407 / ltc1407 a 12-/14-bit, 3msps simultanous sampling adc 3v, 2-channel differential, unipolar inputs, 14mw, msop package ltc1407-1/ltc1407 a -1 12-/14-bit, 3msps simultanous sampling adc 3v, 2-channel differential, bipolar inputs, 14mw, msop package ltc2355 / ltc2356 12-/14-bit, 3.5msps serial adc 3.3v supply, differential input, 18mw, msop package ltc2365 / ltc2366 12-bit, 1msps/3msps serial sampling adc 3.3v supply, 8mw, tsot-23 package amplifiers lt6200 / lt6201 single/dual operational amplifiers 165mhz, 0.95nv/hz lt6230 / lt6231 single/dual operational amplifiers 215mhz, 3.5ma/amplifier, 1.1nv/hz lt6236 / lt6237 single/dual operational amplifier with low wideband noise 215 mhz, 3.5ma/amp, 1.1nv/ hz lt1818 / lt1819 single/dual operational amplifiers 400mhz, 9ma/amplifier, 6nv/hz references ltc6655-2.5/ltc6655-3.3 precision low drift low noise buffered reference 2.5v/3.3v/5v, 5ppm/c, 0.25ppm peak-to-peak noise, msop-8 package l t 1461-3/lt1461-3.3 v precision series voltage family 0.05% initial accuracy, 3ppm drift

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